The present invention is directed to integrated circuit design and test and, more particularly, to a method of validating timing issues in a gate-level simulation of an integrated circuit design.
During the electronic design automation (EDA) design flow of an integrated circuit (IC) having digital (or mixed digital and analog) circuitry, register-transfer-level (RTL) abstraction typically is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of the IC, selecting standard cell designs and their characteristics from a standard cell library. An RTL description is defined in terms of registers that store signal values, and combinational logic that performs logical operations on signal values. The RTL description is usually converted to a gate-level description (such as a netlist) that is used by placement and routing tools to create a physical layout.
The correct operation and performance of the IC is often limited by timing considerations. Static timing analysis (STA) of an IC enables analysis of simplified delay models of the IC and identification of such issues as hold-time and set-up time violations, glitches, and clock skew, using definitions of critical paths and corners. However, STA constraints may be incorrect and may miss some critical paths so dynamic gate-level simulation of the design is often necessary.
Typically dynamic gate-level simulation determines the output values of a gate based on the input values of the gate. If one or more of the input values is indeterminate (that is to say ambiguous), the behavioral model of the simulator may result in an output value of the gate that is also indeterminate. As the simulation progresses, these indeterminate values are propagated from gate to gate to the outputs of a combinational block. The indeterminate values are designated X in some EDA languages. In particular, in VHDL the values ‘U’, ‘X’, ‘W’, and ‘-’ are metalogical values; they define the behavior of the model itself rather than the behavior of the hardware being synthesized, where ‘U’ represents the value of an object before it is explicitly assigned a value during simulation; ‘X’ and ‘W’ represent forcing and weak values, respectively, for which the model is not able to distinguish between logic levels and are distinct from values from a high impedance source or output, designated Z, which may not propagate from gate to gate. The propagation of the indeterminate X values typically cause the simulation to crash, increasing the difficulty of analyzing the cause and position of a timing violation.
When a possible timing violation can be identified as a false timing violation, that is to say one that will not in fact occur in the physical IC, it is possible in some conventional timing simulation techniques to set a parameter called an Xfilter for the standard cell. In this technique, when the Xfilter parameter is set, the model of the identified cell generates an output value corresponding to the cell input value and the theoretical function of the cell. For example, in the case of a D flip flop with a positive edge clock, the model will generate a definite output value equal to the value at the D input at the positive edge of the clock if the Xfilter parameter is set. In addition, all the timing checks for that cell will be disabled, enabling the simulation to proceed without this cell being the cause of the simulation crashing. However, the behavior of the cell in the simulation with the Xfilter parameter set will be unlike the cell in the physical IC. Also the Xfilter disables all the timing checks for that cell, which may mask real timing violations at other points in time. Moreover, in the case of synchronous circuit blocks, it may be difficult to identify whether clock signals are in the same clock domain or not, and validate the possible timing violation, because there may be many buffers in the clock tree, clock gate cells and clock dividers of the same domain.
Identifying and analyzing timing violations and distinguishing real from false timing violations in the IC design can be very labor-intensive and time-consuming. A method of doing so efficiently and with a higher degree of automation is sought.